Business Insider

Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation

SAN JOSE, Calif., Sept. 11, 2017 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its collaboration with TSMC to advance 7nm FinFET Plus design innovation for mobile and ...
Business Wire

Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...
Business Wire

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...
Design-Reuse

Cadence Receives Three TSMC Partner of the Year Awards for Design IP, 16nm FinFET and 3D-IC Solutions

SAN JOSE, Calif. -- October 1, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today received three TSMC Partner of the Year Awards during ...
Digi Times

HiSilicon expands adoption of Cadence tools and IP for advanced-node FinFET designs

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16nm FinFET ...
EDN

Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 16FF+ Process, Companies Collaborate on 10nm FinFET

The Cadence custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design ...
EDN

Cadence Unveils Broad IP Portfolio for New TSMC 16nm FinFET Plus Process

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the ...
Design-Reuse

Cadence Announces Tapeout of 14nm Test-chip with ARM Processor and IBM FinFET Process Technology

14-nanometer SOI FinFET Process Leverages Strong Ecosystem Partnerships Between EDA, Foundry and IP Providers to Deliver Significant Power Savings Potential SAN JOSE, Calif., 30 Oct 2012 - Cadence ...
Nasdaq

Cadence (CDNS) Unveils New UltraLink D2D PHY IP Solutions

Cadence Design Systems, Inc CDNS unveiled UltraLink D2D PHY (physical interfaces) IP for Taiwan Semiconductor Manufacturing Company’s TSM 7 nanometer (nm) FinFET (Fin Field Effect Transistor) process ...
Nasdaq

GLOBALFOUNDRIES and Cadence Add Machine Learning Capabilities to DFM Signoff for GF’s Most Advanced FinFET Solutions

Cadence Litho Physical Analyzer with ML technology qualified for GF 12LP/12LP+ solutions, providing up to 33% greater detection efficiency with less than 10% runtime impact Collaboration between ...
Digi Times

Cadence digital and custom/analog tools achieve TSMC certification for 10nm FinFET early design starts

Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most-current version of 10nm FinFET Design Rule Manual (DRM) and SPICE ...