Business Wire

Mentor Graphics HDL Designer Saves Months of Design Effort with Concurrent HDL Checking

WILSONVILLE, Ore.--(BUSINESS WIRE)--Oct. 7, 2005--Mentor Graphics Corporation (Nasdaq:MENT), the leader in standards-based digital IC design creation, analysis, synthesis, and management tools, today ...
EDN

Mentor extends HDL portfolio with interface design

Mentor Graphics has developed a way of linking intellectual property (IP) cores and HDL modules together in large designs without using code. The company has added the technique to a heavily extended ...
Design-Reuse

The MathWorks and Mentor Graphics Outline Joint DO-254 Workflow for Model-Based Design

NATICK, Mass. and WILSONVILLE, Ore.--March 23, 2010--The MathWorks and Mentor Graphics (NASDAQ: MENT) today announced a joint collaboration to provide guidance on an integrated workflow for DO-254 ...
EDN

Mentor improves HDL suite for ASIC, FPGA designs

SAN MATEO, Calif.—Mentor Graphics Corp. has enhanced its HDL Designer Series front-end design suite to provide better ways to create and manage hardware description languages in ASIC and FPGA designs.
Electronic Design

Mentor Graphics, Mathworks Optimize FPGA Design Flow

Mentor Graphics has upgraded its Precision Synthesis tool to include hardware description language (HDL) generated by MathWorks Simulink HDL Coder. Customers will be able to transfer VHDL and Verilog ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

The Mentor Graphics QVP team fully understood and addressed our needs accurately, enabling us to accelerate our implementation schedule for our products." Bogdan Bizic, SV Verification Product Manager ...
Electronic Design

HDL Design Suite Gains SystemVerilog Support

Today, up to 80% of new ASIC and FPGA designs reuse RTL code from previous designs, and many design teams are embracing SystemVerilog, which was built with design reuse in mind. To support the ongoing ...